1. Field of the Invention
The present invention relates to an operational amplifier circuit and a display apparatus including a display panel driven by the operational amplifier circuit.
2. Description of Related Art
A recent tendency of a flat display panel is toward increase in size. In a TV field, in particular, even a liquid crystal panel exceeding 100 inches has appeared. It is considered that the tendency will be unchanged in the future. On the other hand, as the liquid crystal panel is increased in size, load on a data line in a TFT_LCD (Thin Film Transistor Liquid Crystal Display) increases, and therefore a power consumption amount of an amplifier in an LCD driver for driving the TFT_LCD tends to increase.
In order to reduce the number of LCD drivers to be used, the number of outputs of one chip is increased. For this reason, a power consumption amount of one chip increases, and therefore power consumption of the whole of LCD apparatus increases. The increase in power consumption amount causes a problem of an abnormal increase in chip temperature.
As a measure to such increase in chip temperature, tape to be mounted with the chip is devised to keep a thermal resistance low, or a heat radiating tape is attached to the chip. However, any of them causes cost-up. For this reason, a technique for reducing the power consumption amount in the LCD driver has been required. A large number of amplifiers (operational amplifiers) are used in the LCD driver, and therefore it is important to reduce the power consumption amount of the amplifier, to significantly reduce the power consumption amount of the whole LCD driver.
FIG. 1 is a diagram illustrating a configuration of an operational amplifier circuit as a related art intended to reduce the power consumption amount. The operational amplifier circuit for driving capacitive load (pixel capacitors) on one data line by two operational amplifiers will be described.
Referring to FIG. 1, the operational amplifier circuit includes a positive polarity operational amplifier 10 (Posi_AMP) and a negative polarity operational amplifier 20 (Nega_AMP). An input node 120 of the operational amplifier 10 is supplied with the input signal INP, and an input node 220 of the operational amplifier 20 is supplied with an input signal INN. It should be noted that the input signals INP and INN are analog data signals converted by D/A converters. The D/A converter outputting the input signal INP is driven in a power supply voltage range from VDD/2 to VDD. For this reason, the input signal INP takes a voltage value within a positive polarity voltage range (VDD/2 to VDD). Similarly, the D/A converter outputting the input signal INN is driven within a power supply voltage range of VSS (GND) to VDD/2. For this reason, the input signal INN takes a voltage value within a negative polarity voltage range (VSS (GND) to VDD/2).
The operational amplifier 10 is connected to form a voltage follower, and outputs a positive polarity output signal OUTP (in the positive polarity power supply voltage from VDD/2 to VDD) to an output node 110. A positive polarity power supply node 101 of the operational amplifier 10 is connected to a power supply line VDD and a negative polarity power supply node 102 of the operational amplifier 10 is connected to a power supply line VDD/2 (of the power supply voltage VDD/2). That is, the operational amplifier 10 is applied with voltages in the power supply voltage range from VDD/2 to VDD. The operational amplifier 20 is connected to form a voltage follower, and outputs a negative polarity output signal OUTN (in the negative polarity power supply voltage from VSS (GND) to VDD/2) to an output node 210. A positive polarity power supply node 201 of the operational amplifier 20 is connected to the power supply line VDD/2 (of the power supply voltage VDD/2) and a negative polarity power supply node 202 of the operational amplifier 20 is connected to the power supply line VSS (of the ground voltage GND). That is, the operational amplifier 20 is applied with voltages in the power supply voltage from VSS (GND to VDD/2. The output nodes 110 and 210 are connected to capacitive load (pixel capacitor) through a data line.
FIG. 2 is a circuit diagram illustrating an example of an internal equivalent circuit of the operational amplifier 10. The operational amplifier 10 includes N-channel MOS (NMOS) transistors MN10 and MN20, P-channel MOS (PMOS) transistors MP10, MP20, and MP30, constant current sources I10 and I20, a resistor R10, and a capacitor C10. The NMOS transistors MN10 and MN20 constitute a differential pair in which gates of the transistors MN10 and MN20 are respectively connected to the output node 110 and the input node 120. The PMOS transistors MP10 and MP20 have a function of active load, and configure a Widlar type current mirror. The constant current source I10 supplies a bias current to the differential pair transistors (NMOS transistors MN10 and MN20). The differential pair and the active load form a differential amplifier. A differential signal of the input signal INP and the output signal OUTP is single-converted by the differential amplifier, and then outputted to a gate of the PMOS transistor MP30.
The PMOS transistor MP30 determines a voltage at the output node 110 in accordance with the output from the differential amplifier. At this time, the constant current source I20 functions as active load for the PMOS transistor MP30. Also, the resistor R10 and the capacitor C10 are connected in series between the gate of the PMOS transistor MP30 and the output node 110 to function as a phase compensation circuit.
FIG. 3 is a circuit diagram illustrating an example of an internal equivalent circuit of the operational amplifier 20. The operational amplifier 20 includes NMOS transistors MN30, MN40, and MN50, PMOS transistors MP40 and MP50, constant current sources I30 and 140, a resistor R20, and a capacitor C20. The PMOS transistors MP40 and MP50 configure a differential pair in which gates of the transistors MP40 and MP50 are respectively connected to an output node 210 and an input node 220. The NMOS transistors MN30 and MN40 have a function of active load, and configure a Widlar type current mirror. The constant current source I30 supplies a bias current to the differential pair transistors (PMOS transistors MP40 and MP50). The differential pair and the active load form a differential amplifier. A differential signal of the input signal INN and an output signal OUTN is single-converted by the differential amplifier, and then outputted to a gate of the NMOS transistor MN50.
The NMOS transistor MN50 determines a voltage at the output node 210 in accordance with an output from the differential amplifier. At this time, the constant current source I40 functions as active load for the NMOS transistor MN50. Also, the resistor R20 and the capacitor C20 are connected in series between the gate of the NMOS transistor MN50 and the output node 210 to function as a phase compensation circuit.
The input node 120 of the operational amplifier 10 is supplied with the input signal INP within the positive polarity voltage range (VDD/2 to VDD). For this reason, if the negative polarity power supply node 102 of the operational amplifier 10 is supplied with the power supply voltage VDD/2, the operational amplifier 10 is operable. Similarly, the input node 220 of the operational amplifier 20 is supplied with the input signal INN within the positive polarity voltage range (VSS to VDD/2). For this reason, if the positive polarity power supply node 201 of the operational amplifier 20 is supplied with the power supply voltage VDD/2, the operational amplifier 10 is operable. Accordingly, as illustrated in FIGS. 2 and 3, a part or whole of a current flowing through the negative polarity power supply node 102 in the operational amplifier 10 flows into the positive polarity power supply node 201 of the operational amplifier 20. As a result, the current used in the operational amplifier 10 can be reused in the operational amplifier 20, and therefore a power consumption amount can be reduced.
Also, a detailed operation such as phase compensation in the circuits shown in FIGS. 2 and 3 is described in other literature “Analysis and Design of Analog Integrated Circuits” by Paul R. Gray and Robert G. Meyer (John Wiley & Sons, Inc.), and therefore the detailed description is omitted here.
Further, a technique of a liquid crystal driver using positive and negative polarity operational amplifiers is described in Japanese Patent Application Publication (JP-A-Heisei 10-31200).
By connecting the power supplies for the operational amplifiers as illustrated in FIG. 1, the power consumption amount (in particular, static power consumption) is made approximately half. However, the power supply voltages supplied to the operational amplifiers 10 and 20 are not original voltages (VSS and VDD), and therefore the voltages of the input signals INP and INN are limited. In the operational amplifier 10, since a differential pair is formed from the NMOS transistors MN10 and MN20, a voltage range supplyable to the operational amplifier 10 is from (VDD/2+VGS(MN1)+VDS(sat)) to VDD when VDD/2 is supplied to the negative polarity power supply node 102. Here, VGS(MN1) is a gate-source voltage of the NMOS transistor MN10, and VDS(sat) is a drain-source voltage at a boundary between triode and pentode regions of a MOS transistor constituting the constant current source I10.
Similarly, in the operational amplifier 20, since a differential pair formed from the PMOS transistors MP40 and MP50, a voltage range supplyable to the operational amplifier 20 is from VSS to (VDD/2−VGS(MPL)−VDS(sat)) when VDD/2 is supplied to the positive polarity power supply node 201. Here, VGS(MP1) is a gate-source voltage of the PMOS transistor MP40, and VDS(sat) is a drain-source voltage at a boundary between triode and pentode regions of a MOS transistor constituting the constant current source I30.
For these reasons, a positive polarity voltage of the input signal INP supplied to the operational amplifier 10 is limited to a range of (VDD/2+VGS(MN1)+VDS(sat)) to VDD, and the negative polarity voltage of the input signal INN supplied to the operational amplifier 20 is limited to a range of VSS to (VDD/2−VGS(MP1)−VDS(sat)). Specifically, the voltage of the input signal INP is limited to a range of (VDD/2+1 V) to VDD, and that of the input signal INN is limited to a range of VSS to (VDD/2−1 V). Characteristics required as a typical LCD driver include a range of VDD/2 to (VDD−0.2 V) as the voltage of the input signal INP, and (VSS+0.2 V) to VDD/2 as the voltage of the input signal INN. Therefore, the operational amplifier circuit illustrated in FIG. 1 does not meet the input voltage range (input characteristics) required for an amplifier used in the LCD driver.
When the operational amplifier employs a Rail-to-Rail configuration (not shown), the above-described problem can be solved. In this case, however, there arises a problem that the term of the output deviation specific to the LCD driver is not met. The reason why the problem arises is in that the output deviation is deteriorated based on a change in an operational state of a differential stage near a power supply voltage.